Design for manufacturing

1.Mechanical DFM

Mechanical decisions made in CAD determine unit cost, yield, and cosmetic quality. The expensive failures are the ones the supplier silently absorbs by quoting higher.

1.1Process selection

Match the process to volume, complexity, and cosmetic requirement. Tooling is the dominant variable below ~50 k annual volume.

1.2Plastic resin selection

Five resins cover ~90 % of consumer hardware. Match to use environment, not to cost.

1.3Tolerance grades

ISO 2768 covers general tolerances when none are specified on the drawing. Specify tighter only where it matters.

1.4Injection molding rules

• Wall thicknessNominal 1.5–3.0 mm for most polymers. Uniform within ±50 %. Below 1.2 mm risks short shots; above 3.5 mm risks sinks and 2× cycle time.
• RadiiInternal corners ≥ 0.5× wall thickness. Sharp corners concentrate stress and slow fill; molded radii at 0.5R minimum survive ejection.
• RibsHeight 2–3× wall, base thickness 0.5–0.7× wall, draft 0.5°+. Higher than 3× wall buckles; thicker than 0.7× wall causes sinks on the show surface.
• BossesOuter Ø 2× screw diameter, base radius 0.25× wall. Self-tapping screws need 2.0–2.2× screw OD; heli-coil inserts: 2.5×.
• Gate locationDiscuss with the moulder before CAD lock. Pin-point (small parts), fan/edge (cosmetic), submarine (auto-trim), hot-runner (multi-cavity).
• Cooling timeApprox t = wall² × 0.5 seconds for ABS. A 3 mm wall = 4.5 s cooling; 2× wall = 4× cooling.
• Mold draft0.5°–2° minimum on vertical faces. 3°–5° on textured surfaces (VDI 27+ requires 3°+).

1.5Sheet metal rules

1.6CNC machining rules

2.Electronics DFM

PCB design intent is communicated through Gerbers, drill files, and assembly drawings. DFM at the PCB and assembly level is the difference between 95 % first-pass yield and 75 %.

2.1PCB design rules

2.2Standard layer stacks

Standard impedance reference (50 Ω single-ended, FR-4, 4-layer):

• Trace width: 0.30 mm over 0.20 mm dielectric
• Trace width: 0.10 mm for HDI 4-layer 0.05 mm dielectric
• Verify with manufacturer's impedance calculator (Polar Si9000, supplier's tool).

2.3Component placement

• Component-to-component spacingMinimum 0.5 mm SMD, 1 mm for hand-rework accessibility.
• Orientation consistencyGroup similar components in same orientation to reduce machine-vision verification time and AOI false-positives.
• Polarity markingsCapacitors, diodes, ICs clearly marked on silkscreen.
• Fiducial marksThree global fiducials (preferred) or two diagonal. Local fiducials for 0402 + finer or BGA.
• Test points1.0 mm diameter pads, 2.54 mm spacing for ICT. At least one per net.
• Keep-out zones1 mm around connectors, 2 mm around antennas, 3 mm around shielding cans.

2.4Panelisation

• Panel sizeMatch supplier standard. Common: 18" × 24" (457 × 610 mm) or 250 × 350 mm.
• Routing vs. V-scoringV-scoring for simple rectangles (cheaper, faster). Routing for complex outlines, internal cutouts, or PCBs <1 mm thick.
• Tabs and mouse-bites1.5–2 mm tabs, 4–6 mouse-bites per tab (0.5 mm hole × 0.7 mm spacing).
• Edge rails5–10 mm wide with global fiducials and tooling holes (3.175 mm typical).
• Panel utilisationTarget 70 %+ for cost; below 50 % drives per-board cost up sharply.

2.5Design for test (DFT)

• Test points on every netEspecially power rails, signals, programming interfaces. ICT coverage target: 85 %+ of nets.
• Programming interfaceJTAG, SWD (Cortex), UART, or ISP. Pin header or pogo pad (0.65 mm pitch typical).
• Boundary scanIEEE 1149.1 for complex digital boards (>50 nets).
• Manufacturing test modeFirmware support for self-test (LEDs, sensors, comms, RF self-check).
• Functional test fixturesDesign alongside the product, not after. Budget 2–4 weeks NRE + $3 k–15 k per fixture.

3.Assembly DFM

Assembly is where part count, sequence, and fixturing decisions surface as cost on the production line.

3.1Part-count reduction

• Combine featuresSnap-fit replacing screw + nut; live hinge replacing pin + clip; overmolded grip replacing separate elastomer.
• Eliminate fastenersEach screw is 3–8 s of cycle time. At 10 k units, that's 8–20 hours of line time. At 100 k, that's 80–200 hours.
• Standardise fastenersOne screw type per assembly. Three variants doubles the operator pick-time and inventory.

3.2Assembly sequence

• Linear stackComponents added from one direction. Simpler line, fewer flips, faster cycle.
• Self-aligning featuresAsymmetric mating prevents mis-orientation. Pin-and-slot beats two-bolt symmetric.
• Visual confirmationEach step has a clear visual cue for the operator. Coloured connectors, asymmetric profiles.
• Test gatesFunctional test at each major sub-assembly stage, not just at end of line. Catches 60–80 % of issues earlier.

3.3Line balance + cycle time

Cycle time per station should match. Bottleneck station = UPH (units per hour) ceiling.

3.4Tolerance stack-up example

A 4-part assembly with critical clearance:

• Part A (PC injection): nominal 25.0 mm ± 0.2 mm (process capability ±2σ)
• Part B (sheet metal): nominal 24.5 mm ± 0.1 mm
• Part C (gasket, foam): nominal 0.3 mm ± 0.05 mm
• Part D (PCB thickness): 1.6 mm ± 0.16 mm
• Linear stack: total ±(0.2 + 0.1 + 0.05 + 0.16) = ±0.51 mm
• RSS stack (statistical): √(0.2² + 0.1² + 0.05² + 0.16²) = ±0.28 mm

Linear stack is conservative (worst case); RSS assumes independent normal distributions. Use RSS for ±3σ design, linear for safety-critical clearances.

4.Review checkpoints

DFM is a discipline, not a single review meeting. Apply at four checkpoints.