EMC design and pre-compliance

1.EMC standards

Different standards apply to emission (your device leaking) and immunity (external interference reaching your device). Both must pass for CE / FCC compliance.

1.1Emission standards (radiated + conducted)

1.2Immunity standards

1.3Frequency vs. wavelength reference

Slot apertures > λ/20 act as antennas. At 1 GHz, 1.5 cm slot leaks; at 6 GHz, 2.5 mm slot leaks.

2.Grounding + ground topology

Ground topology determines EMC performance. Most EMC failures trace back to ground design.

2.1Three grounding philosophies

2.2Single ground plane rules

• Solid copper pour on a dedicated layer. No traces, no splits.
• Connect every component ground to the plane through one via per ground pin (more for high-current ICs).
• Adjacent power planes create a low-impedance plane pair that handles return currents naturally.
• Cuts and splits create EMC problemsForces return current to take long paths, increases loop area, radiates strongly.

2.3Common ground topology mistakes

• Splitting ground for "thermal isolation"Creates antenna-like structures. Use thermal vias or copper polyimide instead.
• Cutting ground under fast-edge signalsReturn current diverts to nearest path; loop area grows.
• No chassis-to-PCB ground connectionStatic charge has no return path; ESD damage likely.
• Multiple ground vias far from each otherCreates ground bounce. Add adjacent vias for low impedance.
• Star ground at multiple frequenciesStar is only stable at low frequencies; at RF, requires careful loop design.

2.4Return current behaviour

Every signal trace has a return current that follows the path of least impedance. At high frequencies, this means directly under the signal trace (lowest inductance), not the lowest-resistance path.

A "ground plane" cut under a high-speed trace forces the return current to go around the cut, increasing loop area dramatically and radiating EMI.

3.Shielding

Shielding reduces both emission (containment) and immunity (rejection). Choose based on target frequency and budget.

3.1Shielding strategies

3.2Shielding rules

• Enclose at the sourceShield the noise generator (DC-DC, oscillator, microprocessor), not the rest of the board.
• Slot apertures matterAbove λ/20 they radiate. Maximum slot size at 1 GHz: ~15 mm. At 6 GHz: ~2.5 mm.
• Cable shieldsConnect to chassis at both ends for high-frequency shielding (the lower-frequency loop concern doesn't apply at GHz).
• Vent holesMany small holes radiate less than one large hole. Honeycomb vents reduce leakage further.

3.3Common-mode chokes for cables

USB, audio, and other cables can act as antennas. Common-mode chokes on cable inputs reduce conducted emissions:

• USB CMC0.1 µH (rated at 100 MHz) for USB 2.0/3.0
• Power input CMC1–10 mH for AC power
• Audio CMCPer channel for cleaner audio

4.Filtering + decoupling

Internal filtering at the PCB level catches conducted emissions before they reach cables.

4.1Decoupling cap placement

• One ceramic 100 nF per VCC pin of every IC. Within 5 mm of the pin.
• One bulk cap (1–10 µF) per power-rail bank.
• Multiple ceramics in parallel (10 nF + 100 nF + 1 µF) at high-current IC pins.
• Place caps on the bottom layer adjacent to the IC, with through-hole connection to power plane.

See IDB-PCB-014 for detail on decoupling strategy.

4.2Ferrite beads

Ferrite beads add impedance at RF frequencies while passing DC and low-frequency current.

Ferrite beads on power lines are usually placed at the regulator input/output, not at every IC.

4.3Π-filters

Combine ferrite bead + capacitor for stronger filtering.

`` Ferrite IN ─────┬──────[FB]───┬───── OUT │ │ C₁ (100 nF) C₂ (100 nF) │ │ GND GND ``

Attenuates conducted emissions by 20–40 dB at 100 MHz.

5.ESD protection

ESD = Electrostatic Discharge. The transient is fast (<1 ns rise time) but high amplitude (8–15 kV).

5.1ESD test levels (IEC 61000-4-2)

Level 4 is the typical requirement for consumer products with accessible signals.

5.2ESD protection devices

5.3ESD protection placement

• Place TVS at the connector, not at the IC. Clamps the surge before it propagates.
• TVS to ground via short traceMinimise trace length to reduce inductance.
• Multiple TVS for high pin countDon't bottleneck on one device.

5.4TVS selection criteria

• Standoff voltage (V_R)Must be higher than the maximum normal signal voltage.
• Breakdown voltage (V_BR)Typically 5–25 % above V_R.
• Clamping voltage (V_C) at 8/20 µs pulseThe voltage at which the TVS clamps. Lower V_C = better protection.
• Capacitance (C)Lower C is better for high-speed signals (USB 3.0+ requires <0.5 pF).

5.5Common ESD failure modes

• No TVSIC pin damaged, intermittent or hard failure.
• TVS placed at IC, not at connectorSurge propagates between connector and TVS, can damage trace.
• Insufficient TVS capacityCommon in USB-C where multiple pins need protection.
• Single-pin TVS used on differential pairAsymmetric clamping, can corrupt data.

6.Pre-compliance workflow

Catching EMC issues in-house before formal lab testing saves $3 000–8 000 per failure cycle.

6.1Pre-compliance test setup

A budget pre-compliance setup (~$8 000–15 000) catches 70 % of issues that would otherwise fail formal lab testing.

6.2Pre-scan workflow

1. Power up the DUT (Device Under Test) in worst-case mode (max Wi-Fi traffic, max CPU load, charging, etc.). 2. Measure conducted emissions on power line — Common above 150 kHz to 30 MHz. 3. Measure radiated emissions in a quiet room (ideally semi-anechoic) — 30 MHz to 6 GHz. 4. Compare to standards limits (CISPR 22 / 32 / FCC Part 15 Class B). 5. Identify worst-case bands and frequencies. 6. Apply candidate fixes (filtering, shielding, layout change) and re-measure. 7. Pass/fail decision before booking the lab.

6.3When to schedule pre-compliance

• First proof-of-conceptQuick scan to see worst-case noise.
• Pre-production sampleDefinitive pre-scan; identify all issues.
• Re-test before formal labConfirm all fixes hold.

7.Common EMC failures + fixes

The top 80 % of EMC failures fall into 5 categories.

7.1Conducted emissions on USB power

7.2Radiated emissions 30 MHz – 1 GHz

7.3Radiated emissions > 1 GHz

7.4ESD failure on USB-C

7.5Burst immunity on sensor input